senior physical design engineer


Senior/ Lead Physical Design EngineerRole and ResponsibilitiesImplementation of multimillion gate SoC designs in cutting edge process technologies 65nm, 40nm and 28nmWork on all aspects of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop Static and Dynamic, Signal Integrity Analysis, Physical Verification DRC, ERC, LVS, DFM and DFY and TapeoutClear understanding and command over all aspects of physical design and ultra deep submicron technologiesExperience in ASIC tapeouts, preferably in 65nm and below technology nodesExpertise in Synopsys, Magma or Cadence physical design toolsSkill and experience in scripting using Tcl or Perl is highly desirableFor Lead / Manager Experience in leading and managing teamsRequirements B.
Tech / M.
Tech in Electrical and Electronics / Electronics and Communication with 3 12 years experience in the relevant area