soc design bangalore hyderabad pune


Major Responsibilities The candidate will be responsible for completion of tasks that include place and route, clock tree synthesis, power grid analysis, signal integrity analysis and timing closure.
The candidate must be able to take complete responsibility for the electrically correct completing of high speed hard macros Minimum Qualifications:
   Minimum 2
    *11 years of experience in all aspects of Physical Design Place & Route implementation Experience with taping out FinFET designs usin Bengaluru, Hyderabad, Pune Bengaluru, Hyderabad, Pune